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ADT7476
Table 62. TEMPERATURE LIMIT REGISTERS (Note 1)
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description (Note 2)
Remote 1 Temperature Low Limit
Remote 1 Temperature High Limit
Local Temperature Low Limit
Local Temperature High Limit
Remote 2 Temperature Low Limit
Remote 2 Temperature High Limit
Power-On Default
0x81
0x7F
0x81
0x7F
0x81
0x7F
1. Exceeding any of these temperature limits by 1 ° C causes the appropriate status bit to be set in the interrupt status register. Setting the
Configuration Register 1 Lock bit has no effect on these registers.
2. High limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low limits: An interrupt is generated when a value
is equal to or below its low limit ( ≤ comparison).
Table 63. FAN TACH LIMIT REGISTERS (Note 1)
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
TACH1 Minimum Low Byte
TACH1 Minimum High Byte/Single-channel ADC Channel Select
TACH2 Minimum Low Byte
TACH2 Minimum High Byte
TACH3 Minimum Low Byte
TACH3 Minimum High Byte
TACH4 Minimum Low Byte
TACH4 Minimum High Byte
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
1. Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set
in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 Lock bit has no effect on these registers.
Table 64. REGISTER 0 X55 ? TACH 1 MINIMUM HIGH BYTE (POWER-ON DEFAULT = 0XFF)
Bit No.
[4:0]
[7:5]
Mnemonic
Reserved
SCADC
R/W
Read-only
R/W
Description
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are reserved. Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte.
When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits
are used to select the only channel from which the ADC will take measurements. Otherwise,
these bits represent Bits [7:5] of the TACH1 minimum high byte.
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